1. Field of the Invention
This invention relates to a structure of a memory cell in the memory device, and particularly to memory cell using the variation of the resistance in a polysilicon to store the logic state.
2. Description of Related Art
In the storage of the digital information, the memory capability of a memory device is usually described in a unit of "bit". For a memory device, each unit for storing the data is called a "cell", which conventionally is equivalent to a bit. A memory device has a huge number of memory cells, wherein each memory cell has its own address uniquely. These memory cells are arranged in an array of matrix corresponding to the one coordinate in two indices such as (column, row). Those memory cells have the same column number are interconnected together by one distinct interconnection column line separately. It's similar that those memory cells with the same row number are interconnected together by one distinct interconnection row line.
The memory device is one of semiconductor devices for storing the information or data, and, depending on the functions, is divided into two types: one is read-only-memory (ROM) and the other one is random-access-memory (RAM). The information stored by a ROM would not lost when the power was off but the information stored by a RAM would lost when power was off. Therefore the RAM is a kind of volatile memory.
A RAM is further divided into a static RAM (SRAM) and a dynamic RAM (DRAM). A SRAM is utilizing the conducting properties of the transistors inside the SRAM to store the information, wherein the memory cell is typically composed of six transistors.
Referring to FIG. 1, the FIG. 1 illustrates the configuration of a circuit of a SRAM, which includes two N-channel metal-oxide-semiconductor (NMOS) transistors 100, 102 in depletion mode for the purpose of load, two NMOS transistors 104, 106 in enhancement mode for activating, and two NMOS transistors 108, 110 in enhancement mode for access to the information stored in SRAM. For the transistors 108 and 110, their gates are interconnected by a word line 112 in row sequence, their sources are interconnected by a bit line 114, and their drains are interconnected to the gates of transistor 106 and 104 respectively, in which the sources are grounded together and the drains have been coupled to the transistors 102 and 100 respectively. Therefore the state of "on" or "off" for transistors 104 and 106 is closely related to the switching state of transistors 108 and 110. The drains of the access transistors 104 and 106 are interconnected to the world line voltage source 116.
For both SRAM and ROM, typically, either the switch of the voltage state between high and low on the bit line and word line or the selection of a transistor are used to determine whether the signal is at state of input or output.